At a BIMOS static random access memory (SRAM) is typically characterized by an array of memory cells comprised of MOS transistors and peripheral circuits which include bipolar transistors. In general the bipolar transistors are used for their higher speed characteristics and the MOS transistors are used for their lower power characteristics to obtain both high speed and low power. In SRAMs the bit lines are generally precharged prior to performing a read. One technique, described in U.S. Pat. No. 4,110,840, Abe et al, teaches precharging the bit lines and data lines in response to a complemented write enable signal, i.e., performing a precharge upon the termination of the write mode. The precharge taught is to a voltage level of one N channel threshold voltage below the positive power supply voltage. This is a generally desirable level because it is near the optimum gain of the typical MOS or bipolar sense amplifier and yet is high enough for fairly good cell stability. The cell is more stable and also faster in establishing a given voltage differential on the bit line pair when the bit line voltage is higher. Too high of a voltage is not desirable because the gain of the sense amplifier is reduced. Thus, one N channel threshold voltage below the positive power supply has often been chosen for the precharge voltage. There are some problems with using the threshold voltage of an N channel transistor to reference the bit line voltage. One problem is threshold voltage variation over processing. There is also substantial body effect in using an N channel transistor for precharging the bit lines which substantially increases the drop below the positive power supply voltage provided to the bit lines. This body effect also varies with process variations and power supply voltage. These variations in threshold voltage are not compensated for by either a typical bipolar or a typical MOS sense amplifier.